In the manufacture of very large addressable memories, it is possible that defective regions, including shorts or opens, will appear. For proper use of the memory it is important to detect these defects, whether they be associated with the address lines or data lines, and compensate for them so they do not have an adverse impact on memory operation.
Present random access memory (RAM) architectures provide for data checking either internally or externally with a parity scheme or a higher-order code redundancy technique. These techniques involve adding additional bits to the data word, which can be used to identify, and in some cases correct, errors in the data word. In one such scheme, as the data is read into memory the data bits are also fed into a code generator that produces the additional data bits (or check bits) for error detection and correction. Later, when the data is read from memory the data bits and the appended check bits are input to a code checker. The code checker decodes the check bits and compares the result with the data bits for identification, and in some cases correction, of errors in the data bits.
This data checking system focused on the data words, cannot detect address-related failures. If there is a short, open, or other fault in the address bus structure interconnections or in the individual random access memory microcircuits the code checker described above will not detect it, because data, either correct or incorrect, can be written into or read from the wrong address location with no change in the data itself. Because these address-related defects are reproducible each data read or data write cycle, data could have been written into or read from an incorrect address during execution of a software program.
There is one well known test that can be used during the manufacturing process to locate address-dependent memory failures. This test called address data storage mapping, proceeds as follows:
Step a. Write a unique algorithmically-derived data value to every address. PA1 Step b. Read every address for the unique data value of step a. PA1 Step c. Select a single address, write a different algorithmically-derived unique data value into it (guaranteed different from step a or b). PA1 Step d. Read the address selected in step c to confirm that the unique data from step c is present. PA1 Step e. Read every address to confirm that the unique value from step a remained in every cell, except the step c. selected address. PA1 step f. Repeat steps a through d for every unique address in the address space of the RAM.
This prior art test is an example of a a N**2 test where there are N unique address elements in the RAM such that test execution requires N**2 read operations to the RAM. As memory size increases, the address data storage mapping technique takes progressively longer to find defective address locations. After the address data storage mapping test has identified "bad" address locations, the address decoding mechanism is modified so that data intended for storage at any of the defective cells is rerouted to a good address location. As is well known, this test has certain limitations. The test cannot identify faults that occur only during operational address utilization (including intermittent faults); it is a static test that is inherently limited to off-line use.